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D a t a S h e e t , R e v . 1 . 1 , A p r . 2 00 4
HYS72D32300GBR-[5/ 6/7]-B HYS72D643[ 00/ 20] GBR-[ 5/6/7] -B HYS72D128320GBR-[5/6/ 7]-B
184 - Pi n Regist ered Doubl e Data Rat e SDRAM Modules Reg DIMM DDR SDRAM
M e m or y P r o du c t s
Never
stop
thinking.
Edition 2004-04 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D a t a S h e e t , R e v . 1 . 1 , A p r . 2 00 4
HYS72D32300GBR-[5/6/7]-B HYS72D643[00/20]GBR-[5/6/7]-B HYS72D128320GBR-[5/6/7]-B
184 - Pi n Regist ered Doubl e Data Rat e SDRAM Modules Reg DIMM DDR SDRAM
M e m or y P r o du c t s
Never
stop
thinking.
HYS72D32300GBR-[5/6/7]-B HYS72D643[00/20]GBR-[5/6/7]-B HYS72D128320GBR-[5/6/7]-B HYS72D643[00/20]GBR-[5/6/7]-B HYS72D128320GBR-[5/6/7]-B Revision History: Previous Version: Page 21,22 Rev. 1.1 Rev. 1.0 2004-04 2003-12
Subjects (major changes since last revision) Registerd and PLL current added
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Template: mp_a4_v2.2_2003-10-07.fm
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Table of Contents 1 1.1 1.2 2 3 3.1 3.2 4 5 6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Data Sheet
5
Rev. 1.1, 2004-04
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Overview
1
1.1
* * * * * * * * * *
Overview
Features
* *
184-Pin Registered 8-Byte Dual-In-Line DDR SDRAM Module for "1U" PC, Workstation and Server main memory applications One rank 32M x 72, 64M x 72 and two ranks 64M x 72, 128M x 72 organization JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) with a single + 2.5 V ( 0.2 V) power supply and a single + 2.6 V ( 0.1 V) power supply for DDR400 Built with 256-Mbit DDR-I SDRAMs in P-TFBGA-60-1 packages Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh All inputs and outputs SSTL_2 compatible Re-drive for all input signals using register and PLL devices. Serial Presence Detect with E2PROM Low Profile Modules form factor: 128.95 mm x 28.58 mm x 4.00 mm 133.35 mm x 30.48 mm (1.2") x 4.00 mm (6.80 mm with stacked components) JEDEC standard reference layout for one rank 256MB and 512MB, two ranks 512MB and 1GByte: PC2700 Registered DIMM Raw Cards A,B,C,D Gold plated contacts Performance -5 DDR400B PC3200-3033 -6 DDR333B PC2700-2533 166 166 133 -7 DDR266A PC2100-2033 - 143 133 Unit -- -- MHz MHz MHz
Table 1
Part Number Speed Code Speed Grade Component Module max. Clock Frequency @CL3 @CL2.5 @CL2
fCK3 fCK2.5 fCK2
200 166 133
1.2
Description
The HYS72D[32/64/128]3[00/20]GBR are low profile versions of the standard Registered DIMM modules with less/equal 1.2" inch (30.48 mm) height for 1U Server Applications. The Low Profile DIMM versions are available as 32M x 72 (256MB), 64M x 72 (512MB) and 128M x 72 (1 GB). The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
Data Sheet
6
Rev. 1.1, 2004-04 10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Overview
Table 2 Type
Ordering Information Compliance Code Description SDRAM Technology
PC3200 (CL = 3, tRP = tRCD = 3 at tCK = 5ns) HYS72D32300GBR-5-B HYS72D64300GBR-5-B HYS72D64320GBR-5-B PC3200R-30330-A PC3200R-30330-C PC3200R-30330-B one rank 256 MB Registered DIMM one rank 512 MB Registered DIMM 256 Mbit (x8) 256 Mbit (x4)
two ranks 512 MB Registered 256 Mbit (x8) DIMM two ranks 1 GB Registered DIMM 256 Mbit (x4)
HYS72D128320GBR-5-B PC3200R-30331-D
PC2700 (CL = 2.5, tRP = tRCD = 3 at tCK = 6ns) HYS72D32300GBR-6-B HYS72D64300GBR-6-B HYS72D64320GBR-6-B PC2700R-25330-A PC2700R-25330-C PC2700R-25330-B one rank 256 MB Registered DIMM one rank 512 MB Registered DIMM 256 Mbit (x8) 256 Mbit (x4)
two ranks 512 MB Registered 256 Mbit (x8) DIMM two ranks 1 GB Registered DIMM 256 Mbit (x4)
HYS72D128320GBR-6-B PC2700R-25330-D
PC2100 (CL = 2, tRP = tRCD = 3 at tCK = 7.5ns) HYS72D32300GBR-7-B HYS72D64300GBR-7-B HYS72D64320GBR-7-B PC2100R-20330-A PC2100R-20330-C PC2100R-20330-B one rank 256 MB Registered DIMM one rank 512 MB Registered DIMM 256 Mbit (x8) 256 Mbit (x4)
two ranks 512 MB Registered 256 Mbit (x8) DIMM two ranks 1 GB Registered DIMM 256 Mbit (x4)
HYS72D128320GBR-7-B PC2100R-20330-D
Note: All "product type" end with a place code designating the silicon-die revision. Reference information available on request. Example: HYS72D64300GR-5-B, indicating rev. C dies are used for SDRAM components. The "compliance code" is printed on the module labels describing the speed sort (for example "PC2700"), the latencies and SPD code definition (for example "20330" means CAS latency of 2.0 clocks, RCD1) latency of 3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card used for this module.
1) RCD: Row-Column-Delay
Data Sheet
7
Rev. 1.1, 2004-04 10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Pin Configuration
2
Pin Configuration
Table 3 Pin# Name 125 29 122 27 141 118 115 A6 A7 A8 A9 A10 AP I I I I NC I I NC I I I SSTL SSTL SSTL SSTL SSTL SSTL SSTL - SSTL SSTL SSTL Clock Signal Complement Clock Clock Enable Rank 0 Clock Enable Rank 1 Note: 2-rank module NC Note: 1-rank module Chip Select of Rank 0 Chip Select of Rank 1 Note: 2-ranks module NC Note: 1-rank module Row Address Strobe Column Address Strobe Write Enable NC NC - 167 NC A13 NC I - SSTL A11 A12 Pin Configuration of RDIMM (cont'd) Pin Buffer Function Type Type I I I I I I I I SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Address Signal 12 Note: Module based on 256 Mbit or larger dies Note: 128 Mbit based module Address Signal 13 Note: 1 Gbit based module Note: Module based on 512 Mbit or smaller dies Address Bus 11:0
The pin configuration of the Registered DDR SDRAM DIMM is listed by function in Table 3 (184 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 4 and Table 5 respectively. The pin numbering is depicted in Figure 1. Table 3 Pin# Name Clock Signals 137 138 21 111 CK0 CK0 CKE0 CKE1 Pin Configuration of RDIMM Pin Buffer Function Type Type
Control Signals 157 158 S0 S1
154 65 63 10
RAS CAS WE
RESET I
LVRegister Reset CMOS Forces registered inputs low Note: For detailed description of the Power Up and Power Management see the Application Note at the end of data sheet
Address Signals 59 52 48 43 41 130 37 32 BA0 BA1 A0 A1 A2 A3 A4 A5 I I I I I I I I SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Address Bus 11:0 Bank Address Bus 1:0 Address Bus 11:0
Data Sheet
8
Rev. 1.1, 2004-04 10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Pin Configuration Table 3 Pin# Name Data Signals 2 4 6 8 94 95 98 99 12 13 19 20 105 106 109 110 23 24 28 31 114 117 121 123 33 35 39 40 126 127 131 133 53 55 57 60 146 147 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Bus 63:0 Pin Configuration of RDIMM (cont'd) Pin Buffer Function Type Type Table 3 Pin# Name 150 151 61 64 68 69 153 155 161 162 72 73 79 80 165 166 170 171 83 84 87 88 174 175 178 179 44 45 49 51 134 135 142 144 5 14 25 36 56 67 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 Pin Configuration of RDIMM (cont'd) Pin Buffer Function Type Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Strobes 8:0 Note: See block diagram for corresponding DQ signals Check Bits 7:0 Data Bus 63:0
Data Sheet
9
Rev. 1.1, 2004-04 10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Pin Configuration Table 3 Pin# Name 78 86 47 97 DQS6 DQS7 DQS8 DM0 DQS9 107 DM1 Pin Configuration of RDIMM (cont'd) Pin Buffer Function Type Type I/O I/O I/O I I/O I SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Mask 0 Note: x8 based module Data Strobe 9 Note: x4 based module Data Mask 1 Note: x8 based module DQS10 I/O 119 DM2 I Data Strobe 10 Note: x4 based module Data Mask 2 Note: x8 based module DQS11 I/O 129 DM3 I Data Strobe 11 Note: x4 based module Data Mask 3 Note: x8 based module DQS12 I/O 149 DM4 I Data Strobe 12 Note: x4 based module Data Mask 4 Note: x8 based module DQS13 I/O 159 DM5 I Data Strobe 13 Note: x4 based module Data Mask 5 Note: x8 based module DQS14 I/O 169 DM6 I Data Strobe 14 Note: x4 based module Data Mask 6 Note: x8 based module DQS15 I/O 177 DM7 I Data Strobe 15 Note: x4 based module Data Mask 7 Note: x8 based module DQS16 I/O 140 DM8 I Data Strobe 16 Note: x4 based module Data Mask 8 Note: x8 based module DQS17 I/O Data Strobe 17 Note: x4 based module 15, VDDQ 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 7, VDD 38, 46, 70, 85, 108, 120, 148, 168 PWR - Data Strobes 8:0 Table 3 Pin# Name EEPROM 92 91 181 182 183 1 184 SCL SDA SA0 SA1 SA2 I I/O I I I CMOS Serial Bus Clock OD Serial Bus Data CMOS Slave Address Select CMOS Bus 2:0 CMOS I/O Reference Voltage EEPROM Power Supply I/O Driver Power Supply Pin Configuration of RDIMM (cont'd) Pin Buffer Function Type Type
Power Supplies
VREF AI - VDDSPD PWR -
PWR -
Power Supply
Data Sheet
10
Rev. 1.1, 2004-04 10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Pin Configuration Table 3 Pin# Name Pin Configuration of RDIMM (cont'd) Pin Buffer Function Type Type GND - Ground Plane
Table 4 I O I/O AI PWR GND NU NC
Abbreviations for Pin Type Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Usable (JEDEC Standard) Not Connected (JEDEC Standard)
Abbreviation Description
VSS 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176
Other Pins 82
Table 5 SSTL LV-CMOS
Abbreviations for Buffer Type Serial Stub Terminalted Logic (SSTL2) Low Voltage CMOS CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
Abbreviation Description
CMOS
OD
VDDID
O
OD
VDD Identification
Note: Pin in tristate, indicating VDD and VDDQ nets connected on PCB
NC 9, 16, 17, 71, 75, 76, 90, 101, 102, 103, 113, 163, 173
NC
-
Not connected Pins not connected on Infineon RDIMM's
Data Sheet
11
Rev. 1.1, 2004-04 10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Pin Configuration
Front View
Standard Height
PIN 1
PIN 52
PIN 53
PIN 92
Back View
PIN 93 PIN 144 PIN 145 PIN 184
Front View
1U Height
PIN 1
PIN 52
PIN 53
PIN 92
Back View
PIN 93 PIN 144 PIN 145 PIN 184
Figure 1
PCB with Pin Connector
Data Sheet
12
Rev. 1.1, 2004-04 10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Pin Configuration
Table 6 Density
Address Format Organization Memory Ranks SDRAMs # of SDRAMs # of row/bank/ columns bits 13 / 2 / 10 13 / 2 / 11 13 / 2 / 10 13 / 2 / 11 Refresh Period Interval
256 MB 512 MB 512 MB 1 GB
32M x 72 64M x 72 64M x 72 128M x 72
1 1 2 2
32M x8 64M x4 32M x8 64M x4
9 18 18 36
8K 8K 8K 8K
64 ms 64 ms 64 ms 64 ms
7.8 s 7.8 s 7.8 s 7.8 s
Data Sheet
13
Rev. 1.1, 2004-04 10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Pin Configuration
RS0 DQS0 DM0/DQS9
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D0 DQS
DQS4 DM4/DQS13
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D4 DQS
DQS1 DM1/DQS10
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D1
DQS5 DM5/DQS14
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D5
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D2 DQS
DQS6 DM6/DQS15
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D6 DQS
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D3 DQS
DQS7 DM7/DQS16
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D7
DQS8 DM8/DQS17
VDDSPD Serial PD CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D8 DQS SDA SCL A0 A1 A2 VDD, V DDQ VREF V SS V DDID
EEPROM D0 - D8 D0 - D8 D0 - D8 D0 - D8 Strap: see Note 4
SA0 SA1 SA2
CS0 BA0-BA1 A0-A12 RAS CAS CKE0 WE PCK PCK
R E G I S T E R
RS0 -> CS : SDRAMs D0-D8 RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D8 RA0-RA12 -> A0-A12: SDRAMs D0 - D8 RRAS -> RAS : SDRAMs D0 - D8 RCAS -> CAS : SDRAMs D0 - D8 RCKE0 -> CKE: SDRAMs D0 - D8 RWE -> WE : SDRAMs D0 - D8 CK0, CK 0 --------- PLL* * Wire per Clock Loading Table/Wiring Diagrams
Notes: 1. DQ-to-I/O wiring may be changed within a byte. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, Adress and control resistors: 22 Ohms. 4. VDDID strap connections STRAP OUT (OPEN): VDD = VDDQ 5. SDRAM placement alternates between the back and front of the DIMM.
RESET
Figure 2
Block Diagram: One Rank 32M x 72 DDR SDRAM DIMM Module (32Mx8 components) HYS72D32300GBR on Raw Card A
Data Sheet
14
Rev. 1.1, 2004-04 10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Pin Configuration
RS1 RS0 DQS0 DM0/DQS9
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D0 DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D9
DQS4 DM4/DQS13
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D4 DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D13 DQS
DQS1 DM1/DQS10
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D1 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D10
DQS5 DM5/DQS14
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D5 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D14
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D2 DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D11 DQS
DQS6 DM6/DQS15
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D6 DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D15 DQS
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D3 DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D12 DQS
DQS7 DM7/DQS16
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 Serial PD DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D8 DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D17 DQS SCL A0 A1 A2 SDA V DD, V DDQ VREF V SS V DDID D0 - D17 D0 - D17 D0 - D17 Strap: see Note 4 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D16
DQS8 DM8/DQS17
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 CS0 CS1 BA0-BA1 A0-A12 RAS CAS CKE0 CKE1 WE PCK PCK
VDDSPD
EEPROM
SA0 SA1 SA2
CK0, CK 0 --------- PLL* RS0 -> CS : SDRAM D0-D8 RS1 -> CS : SDRAM D9-D17 RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D17 RA0-RA12 -> A0-A12: SDRAMs D0 - D17 RRAS -> RAS : SDRAMs D0 - D17 RCAS -> CAS : SDRAMs D0 - D17 RCKE0 -> CKE: SDRAMs D0 - D8 RCKE1 -> CKE: SDRAMs D9 - D17 RWE -> WE : SDRAMs D0 - D17 RESET * Wire per Clock Loading Table/Wiring Diagrams
R E G I S T E R
Notes: 1. DQ-to-I/O wiring may be changed within a byte. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, Adress and control resistors: 22 Ohms. 4. VDDID strap connections STRAP OUT (OPEN): VDD = VDDQ 5. SDRAM placement alternates between the back and front of the DIMM.
Figure 3
Block Diagram: Two Ranks 64M x 72 DDR-I SDRAM DIMM Module (32Mx8 components) HYS 72D64320GBR on Raw Card B 15 Rev. 1.1, 2004-04 10102003-01E2-HPA8
Data Sheet
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Pin Configuration
VSS RS0B RS0A DQS0
DQS DQ0 DQ1 DQ2 DQ3 I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS D0 DM
DM0/DQS9
DQ4 DQ5 DQ6 DQ7 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS D9 DM
DQS1
CS D1 DM DQ8 DQ9 DQ10 DQ11
DM1/DQS10
DQ12 DQ13 DQ14 DQ15 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS D10 DM
DQS2
CS D2 DM DQ16 DQ17 DQ18 DQ19
DM2/DQS11
CS D11 DM DQ20 DQ21 DQ22 DQ23
DQS3
DM3/DQS12
CS D3 DM DQ28 DQ29 DQ30 DQ31 CS D12 DM DQ24 DQ25 DQ26 DQ27
DQS4
DQ32 DQ33 DQ34 DQ35 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS DQ56 DQ57 DQ58 DQ59 I/O 0 I/O 1 I/O 2 I/O 3 DQS CB0 CB1 CB2 CB3 CS0 BA0-BA1 A0-A11,A12 RAS CAS CKE0 WE PCK PCK I/O 0 I/O 1 I/O 2 I/O 3 CS D4 DM
DM4/DQS13
DQ36 DQ37 DQ38 DQ39
CS D13
DM
V DDSPD
EEPROM
VDD, VDDQ VREF V SS
D0 - D17 D0 - D17 D0 - D17 Strap: see Note 4
DQS5
CS D5 DM DQ40 DQ41 DQ42 DQ43
DM5/DQS14
DQ44 DQ45 DQ46 DQ47
CS D14
DM
V DDID
DQS6
DQ48 DQ49 DQ50 DQ51
CS D6
DM
DM6/DQS15
DQ52 DQ53 DQ54 DQ55
Serial PD DM SCL A0 A1 A2 SDA
CS DQS I/O 0 I/O 1 D15 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS D16
SA0 SA1 SA2
DQS7
CS D7 DM
DM7/DQS16
DQ60 DQ61 DQ62 DQ63 DM
DM
Notes: 1. DQ-to-I/O wiring may be changed within a byte. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, Adress and control resistors: 22 Ohms. 4. VDDID strap connections STRAP OUT (OPEN): VDD = VDDQ 5. SDRAM placement alternates between the back and front of the DIMM.
DQS8
CS D8
DM8/DQS17
CB4 CB5 CB6 CB7
CS D17
DM
R E G I S T E R
RS 0 -> CS : SDRAMs D0-D17
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D17 RA0-RA11,RA12 -> A0-A11,A12: SDRAMs D0 - D17 RRAS -> RAS : SDRAMs D0 - D17 RCAS -> CAS : SDRAMs D0 - D17 RCKE0A -> CKE: SDRAMs D0 - D8 RCKEB -> CKE: SDRAMs D9 - D17 CK0, CK 0 --------- PLL* RWE -> WE : SDRAMs D0 - D17 * Wire per Clock Loading Table/Wiring Diagrams RESET
Figure 4
Block Diagram: One Rank 64M x 72 DDR-I SDRAM DIMM Modules (64Mx4 components) HYS72D64300GBR on Raw Card C 16 Rev. 1.1, 2004-04 10102003-01E2-HPA8
Data Sheet
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Pin Configuration
VSS RS1 RS0 DQS0
DQ0 DQ1 DQ2 DQ3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM
DM0/DQS9
D0
DQS I/O 3 I/O 2 I/O 1 I/O 0 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQ4 DQ5 DQ6 DQ7
D18
DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
DM
D9
DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
DM
D27
DQS1
CS DM CS DM DQ8 DQ9 DQ10 DQ11
DM1/DQS10
CS DM CS DM
D1
D19
DQ12 DQ13 DQ14 DQ15
D10
D28
DQS2
CS DM CS DM DQ16 DQ17 DQ18 DQ19
DM2/DQS11
CS DM CS DM
D2
D20
DQ20 DQ21 DQ22 DQ23
D11
D29
DQS3
DQ24 DQ25 DQ26 DQ27
DM3/DQS12
CS DM CS DM DQ28 DQ29 DQ30 DQ31 CS DM CS DM
D3
D21
D12
D30
DQS4
DQ32 DQ33 DQ34 DQ35 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM CS DM
DM4/DQS13
D4 D22
DQ36 DQ37 DQ38 DQ39 DM
CS
DM
CS
DM
D13
D31
DQS5
CS DM CS DQ40 DQ41 DQ42 DQ43
DM5/DQS14
DQ44 DQ45 DQ46 DQ47
CS
DM
DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
DM
D5
D23
D14
D32
DQS6
DQ48 DQ49 DQ50 DQ51
CS
DM
CS
DM
DM6/DQS15
DQ52 DQ53 DQ54 DQ55
CS
DM
D6
D24
D15
DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
DM
D33
DQS7
CS DM CS DM DQ56 DQ57 DQ58 DQ59
DM7/DQS16
CS
DM
CS
DM
D7
D25
DQ60 DQ61 DQ62 DQ63 DM
D16
D34
DQS8
CS DM CS CB0 CB1 CB2 CB3
DM8/DQS17
CS CB4 CB5 CB6 CB7
DM
CS
DM
D8
D26
D17
D35
CK0, CK0 --------- PLL* * Wire per Clock Loading Table/Wiring Diagrams S0 S1 BA0-BA1 A0-A12 RAS CAS CKE0 CKE1 WE PCK PCK
Serial PD SCL WP A0 A1 A2
VDDSPD
R E G I S T E R
RSO -> CS : SDRAMs D0-D17 RS1 -> CS: SDRAMs D18-D35 RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D35 RA0-RA12 -> A0-A12: SDRAMs D0- D35 RRAS -> RAS: SDRAMs D0-D35 RCAS -> CAS: SDRAMs D0-D35 RCKE0 -> CKE: SDRAMs D0-D17 RCKE1 -> CKE: SDRAMs D18-D35 RWE -> WE: SDRAMs D0-D35 RESET
SA0 SA1 SA2
VDDQ SDA VDD VREF VSS VDDID
Serial PD D0-D35 D0-D35 D0-D35 D0-D35 Strap: see Note 4
Notes:
1. DQ-to-I/O wiring may be changed within a byte. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ/DQS resistors should be 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD VDDQ. 5. Address and control resistors should be 22 Ohms. 6. Each Chip Select and CKE pair alternate between decks for thermal enhancement.
Figure 5
Block Diagram: Two Ranks 128M x 72 DDR SDRAM DIMM Modules (64Mx4 components) HYS72D128320GBR on Raw Card D 17 Rev. 1.1, 2004-04 10102003-01E2-HPA8
Data Sheet
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Electrical Characteristics
3
3.1
Table 7 Parameter
Electrical Characteristics
Operating Conditions
Absolute Maximum Ratings Symbol min. Values typ. - - - - - - 2.0 50 max. -0.5 -0.5 -0.5 -0.5 0 -55 - - Unit Note/ Test Condition V V V V C C W mA - - - - - - - -
Voltage on I/O pins relative to VSS Voltage on inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating temperature (ambient) Storage temperature (plastic) Power dissipation (per SDRAM component) Short circuit output current
VIN, VOUT VIN VDD VDDQ TA TSTG PD IOUT
VDDQ +
0.5 +3.6 +3.6 +3.6 +70 +150 - -
Attention: Permanent damage to the device may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. Table 8 Parameter Device Supply Voltage Device Supply Voltage Electrical Characteristics and DC Operating Conditions Symbol Min. Values Typ. 2.5 2.6 2.5 2.6 2.5 Max. 2.7 2.7 2.7 2.7 3.6 0 V V V V V V 2.3 2.5 2.3 2.5 2.3 0 Unit Note/Test Condition 1)
VDD
VDD Output Supply Voltage VDDQ Output Supply Voltage VDDQ EEPROM supply voltage VDDSPD Supply Voltage, I/O Supply VSS, Voltage VSSQ Input Reference Voltage VREF I/O Termination Voltage VTT
(System) Input High (Logic1) Voltage VIH(DC) Input Low (Logic0) Voltage VIL(DC) Input Voltage Level, CK and CK Inputs Input Differential Voltage, CK and CK Inputs VI-Matching Pull-up Current to Pull-down Current
fCK 166 MHz fCK > 166 MHz 2) fCK 166 MHz 3) fCK > 166 MHz 2)3)
-- --
4) 5)
0.49 x VDDQ 0.5 x VDDQ 0.51 x VDDQ V
VREF - 0.04 VREF + 0.15
-0.3 -0.3 0.36 0.71
VREF + 0.04 V VDDQ + 0.3 V VREF - 0.15 V VDDQ + 0.3 V VDDQ + 0.6
1.4 V --
8) 8) 8)
VIN(DC) VID(DC)
VIRatio
8)6)
7)
Data Sheet
18
Rev. 1.1, 2004-04 10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Electrical Characteristics Table 8 Parameter Input Leakage Current Electrical Characteristics and DC Operating Conditions (cont'd) Symbol Min. Values Typ. Max. 2 A Any input 0 V VIN VDD; All other pins not under test = 0 V 8)9) DQs are disabled; 0 V VOUT VDDQ -2 Unit Note/Test Condition 1)
II
Output Leakage Current Output High Current, Normal Strength Driver Output Low Current, Normal Strength Driver
1) 0 C TA 70 C
IOZ IOH IOL
-5 -- 16.2
5 -16.2 --
A mA mA
VOUT = 1.95 V VOUT = 0.35 V
2) DDR400 conditions apply for all clock frequencies above 166 MHz 3) Under all conditions, VDDQ must be less than or equal to VDD. 4) Peak to peak AC noise on VREF may not exceed 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. 5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 6) VID is the magnitude of the difference between the input level on CK and the input level on CK. 7) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 8) Inputs are not recognized as valid until VREF stabilizes. 9) Values are shown per DDR SDRAM component
Data Sheet
19
Rev. 1.1, 2004-04 10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Electrical Characteristics
Table 9
IDD Specifications
HYS72D128320GBR-5-B HYS72D32300GBR-5-B HYS72D64300GBR-5-B HYS72D64320GBR-5-B Unit Note/ Test Conditions5)
Product Type & Organisation
256 MB x72 1 Rank -5 typ. max. 1960 2005 725 1139 932 869 1319 2185 2194 2635 671 3310 1690 1825 698 1076 878 815 1238 2005 2005 2320 656.6 3040
512 MB x72 1 Rank -5 typ. 2500 2770 752 1508 1112 986 1832 3130 3130 3760 669.2 5200 max. 3040 3130 806 1634 1220 1094 1994 3490 3508 4390 698 5740
512 MB x72 2 Ranks -5 typ. 2284 2419 752 1508 1112 986 1832 2599 2599 2914 669.2 3634 max. 2599 2644 806 1634 1220 1094 1994 2824 2833 3274 698 3949
1 GByte x72 2 Ranks -5 typ. 3688 3958 860 2372 1580 1328 3020 4318 4318 4948 694.4 6388 max. 4318 4408 968 2624 1796 1544 3344 4768 4786 5668 752 7018 mA mA mA mA mA mA mA mA mA mA mA mA
1)4) 1)3)4) 2)4) 2)4) 2)4) 2)4) 2)4) 1)3)4) 1)4) 1)4) 2)4) 1)3)4)5)
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) The module IDD values are calculated from the component IDD datasheet values are: n * IDDx[component] for single bank modules (n: number of components per module bank) n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank) 2) The module IDD values are calculated from the component IDD datasheet values are: n * IDDx[component] for single bank modules (n: number of components per module bank) 2 * n * IDDx[component] for single two bank modules (n: number of components per module bank) 3) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 4) Module IDD is calculated on the basis of component IDD and includes Register and PLL 5) Test condition for maximum values: VDD = 2.7 V, TA = 10 C
Data Sheet
20
Rev. 1.1, 2004-04 10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Electrical Characteristics
Table 10
IDD Specifications
HYS72D128320GBR-6-B HYS72D32300GBR-6-B HYS72D64300GBR-6-B HYS72D64320GBR-6-B Unit Note/ Test Conditions5)
Product Type & Organisation
256 MB x72 1 Rank -6 typ. max. 1720 1810 511 925 682 619 1015 1990 2035 2440 453 3160 1495 1630 484 835 652 592 970 1720 1855 2022 444 2600
512 MB x72 1Ranks -6 typ. 2260 2530 538 1240 875 754 1510 2710 2980 3313 457 4470 max. 2710 2890 592 1420 934 808 1600 3250 3340 4150 475 5590
512 MB x72 2 Ranks -6 typ. 2035 2170 538 1240 875 754 1510 2260 2395 2562 457 3140 max. 2305 2395 592 1420 934 808 1600 2575 2620 3025 475 3745
1 GB x72 2 Ranks -6 typ. 3340 3610 646 2050 1319 1078 2590 3790 4060 4393 484 5550 max. 3880 4060 754 2410 1438 1186 2770 4420 4510 5320 520 6760 mA mA mA mA mA mA mA mA mA mA mA mA
1)4) 1)3)4) 2)4) 2)4) 2)4) 2)4) 2)4) 1)3)4) 1)4) 1)4) 2)4) 1)3)4)5)
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) The module IDD values are calculated from the component IDD datasheet values are: n * IDDx[component] for single bank modules (n: number of components per module bank) n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank) 2) The module IDD values are calculated from the component IDD datasheet values are: n * IDDx[component] for single bank modules (n: number of components per module bank) 2 * n * IDDx[component] for single two bank modules (n: number of components per module bank) 3) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 4) Module IDD is calculated on the basis of component IDD and includes Register and PLL 5) Test condition for maximum values: VDD = 2.7 V, TA = 10 C
Data Sheet
21
Rev. 1.1, 2004-04 10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Electrical Characteristics
Table 11
IDD Specifications
HYS72D128320GBR-7-B HYS72D32300GBR-7-B HYS72D64300GBR-7-B HYS72D64320GBR-7-B Unit Note/ Test Conditions5)
Product Type & Organisation
256 MB x72 1 Rank -7 typ. max. 1488 1578 448 736 601 538 871 1623 1713 2208 399 2613 1263 1398 426 691 556 511 826 1443 1533 1803 390 2128
512 MB x72 1 Rank -7 typ. 1938 2208 475 1006 736 646 1276 2298 2478 3018 403 3668 max. 2388 2568 520 1096 826 700 1366 2658 2838 3828 421 4638
512 MB x72 2 Ranks -7 typ. 1713 1848 475 1006 736 646 1276 1893 1983 2253 403 2578 max. 1983 2073 520 1096 826 700 1366 2118 2208 2703 421 3108
1 GB x72 2 Ranks -7 typ. 2838 3108 574 1636 1096 916 2176 3198 3378 3918 430 4568 max. 3378 3558 664 1816 1276 1024 2356 3648 3828 4818 466 5628 mA mA mA mA mA mA mA mA mA mA mA mA
1)4) 1)3)4) 2)4) 2)4) 2)4) 2)4) 2)4) 1)3)4) 1)4) 1)4) 2)4) 1)3)4)5)
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) The module IDD values are calculated from the component IDD datasheet values are: n * IDDx[component] for single bank modules (n: number of components per module bank) n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank) 2) The module IDD values are calculated from the component IDD datasheet values are: n * IDDx[component] for single bank modules (n: number of components per module bank) 2 * n * IDDx[component] for single two bank modules (n: number of components per module bank) 3) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 4) Module IDD is calculated on the basis of component IDD and includes Register and PLL 5) Test condition for maximum values: VDD = 2.7 V, TA = 10 C
Data Sheet
22
Rev. 1.1, 2004-04 10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Electrical Characteristics
3.2
Table 12 Parameter
AC Characteristics
AC Timing - Absolute Specifications -5/-6/-7 Symbol Min. -5 DDR400B Max. +0.7 +0.6 0.55 0.55 8 12 12 -- -- -- -- +0.7 +0.7 1.25 +0.4 +0.5 -- -- -- -- -- -- 0.6 -- Min. -0.7 -0.6 0.45 0.45 -- 6 7.5 0.45 0.45 2.2 1.75 -- -0.7 0.75 -- -- -6 DDR333 Max. +0.7 +0.6 0.55 0.55 -- 12 12 -- -- -- -- +0.7 +0.7 1.25 +0.4 +0.55 -- -- -- -- -- -- 0.6 -- Min. -7 DDR266A Max. ns ns
2)3)4)5)
Unit Note/ Test Condition 1)
DQ output access time from CK/CK
tAC
-0.7 -0.6 0.45 0.45 5 6 7.5
-0.75 +0.75 -0.75 +0.75 0.45 0.45 -- 7.5 7.5 0.5 0.5 2.2 1.75 -- 0.55 0.55 -- 12 12 -- -- -- -- +0.75
DQS output access time from tDQSCK CK/CK CK high-level width CK low-level width Clock Half Period Clock cycle time
2)3)4)5)
tCH tCL tHP tCK
tCK tCK
ns ns ns ns ns ns ns ns ns
2)3)4)5) 2)3)4)5) 2)3)4)5)
min. (tCL, tCH)
min. (tCL, tCH)
min. (tCL, tCH) ns
CL = 3.0 2)3)4)5) CL = 2.5 2)3)4)5) CL = 2.0 2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5)6)
tDH DQ and DM input setup time tDS Control and Addr. input pulse tIPW
DQ and DM input hold time width (each input) DQ and DM input pulse width tDIPW (each input) Data-out high-impedance time tHZ from CK/CK Data-out low-impedance time tLZ from CK/CK Write command to 1st DQS latching transition DQS-DQ skew (DQS and associated DQ signals) Data hold skew factor DQ/DQS output hold time DQS input low (high) pulse width (write cycle)
0.4 0.4 2.2 1.75 -- -0.7 0.72 -- --
2)3)4)5)6)
2)3)4)5)7)
-0.75 +0.75 0.75 -- 1.25 +0.5
2)3)4)5)7)
tDQSS tDQSQ tQHS tQH tDQSL,H
tCK
ns
2)3)4)5)
TFBGA 2)3)4)5) TFBGA 2)3)4)5)
2)3)4)5)
+0.75 ns
tHP - tQHS
0.35 0.2 0.2 2 0 0.4 0.25
tHP - tQHS
0.35 0.2 0.2 2 0 0.4 0.25
tHP - tQHS
0.35 0.2 0.2 2 0 0.4 0.25
-- -- -- -- -- -- 0.6 --
ns
tCK tCK tCK tCK
ns
2)3)4)5)
DQS falling edge to CK setup tDSS time (write cycle) DQS falling edge hold time from CK (write cycle) Mode register set command cycle time Write preamble setup time Write postamble Write preamble
2)3)4)5)
tDSH tMRD tWPRES tWPST tWPRE
2)3)4)5)
2)3)4)5)
2)3)4)5)8) 2)3)4)5)9) 2)3)4)5)
tCK tCK
Data Sheet
23
Rev. 1.1, 2004-04 10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Electrical Characteristics Table 12 Parameter AC Timing - Absolute Specifications -5/-6/-7 (cont'd) Symbol Min. Address and control input setup time -5 DDR400B Max. -- -- Min. 0.75 0.8 0.75 0.8 1.1 0.6 0.9 0.4 60 72 -- -- 18 18 -6 DDR333 Max. -- -- -- -- 1.1 0.6 -- -- -- -- Min. 0.9 1.0 0.9 1.0 0.90 0.4 65 75 20 20 -7 DDR266A Max. -- -- -- -- 1.1 0.6 -- -- -- -- ns ns ns ns fast slew rate
3)4)5)6)10)
Unit Note/ Test Condition 1)
tIS
0.6 0.7
slow slew rate
3)4)5)6)10)
Address and control input hold tIH time
0.6 0.7
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
tRPRE Read postamble tRPST Active to Precharge command tRAS Active to Active/Auto-refresh tRC
Read preamble command period Auto-refresh to Active/Autorefresh command period Active to Read or Write delay
0.9 0.4 40 55 65 15 15
tCK tCK
ns ns ns ns ns ns ns
70E+3 42
70E+3 45
70E+3 ns
tRFC
2)3)4)5)
tRCD Precharge command period tRP Active to Autoprecharge delay tRAP
Active bank A to Active bank B tRRD command
2)3)4)5) 2)3)4)5) 2)3)4)5)
tRCD or tRASmin
10 15 -- 2 75 200 -- -- -- -- 7.8 -- --
tRCD or tRASmin
12 15 -- 1 75 200 -- -- -- -- 7.8 -- --
tRCD or -- tRASmin
15 15 -- 1 75 200 -- -- -- -- 7.8 -- --
2)3)4)5)
tWR Auto precharge write recovery tDAL
Write recovery time + precharge time Internal write to read command delay Exit self-refresh to non-read command Exit self-refresh to read command Average Periodic Refresh Interval
2)3)4)5) 2)3)4)5)11)
tCK tCK
ns
tWTR tXSNR tXSRD tREFI
2)3)4)5)
2)3)4)5)
tCK
s
2)3)4)5)
2)3)4)5)12)
1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V (DDR333); VDDQ = 2.6 V 0.1 V, VDD = +2.6 V 0.1 V (DDR400) 2) Input slew rate 1 V/ns for DDR400, DDR333 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) These parameters guarantee device timing, but they are not necessarily tested on each device. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
Data Sheet
24
Rev. 1.1, 2004-04 10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Electrical Characteristics
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VOH(ac) and VOL(ac). 11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
25
Rev. 1.1, 2004-04 10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
SPD Contents
4
Table 13
SPD Contents
SPD Codes for HYS72D128320GBR-5, HYS72D643[00/20]GBR-5 and HYS72D32300GBR-5 HYS72D128320GBR-5-B HYS72D64300GBR-5-B HYS72D64320GBR-5-B HYS72D32300GBR-5-B 256 MB x72 1 Rank Rev 0.0 HEX 80 08 07 0D 0A 01 48 00 04 50 50 02 82 08 08 01 Rev. 1.1, 2004-04 10102003-01E2-HPA8
Product Type & Organization
1 GByte x72 2 Ranks PC3200R-30331 HEX 80
512 MB x72 1 Rank PC3200R-30330 Rev 0.0 HEX 80 08 07 0D 0B 01 48 00 04 50 50 02 82 04 04 01
512 MB x72 2 Ranks Rev 0.0 HEX 80 08 07 0D 0A 02 48 00 04 50 50 02 82 08 08 01
Label Code Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Description Programmed SPD Bytes in E2PROM
PC3200R-30330 PC3200R-30330
Jedec SPD Revision Rev 1.0
Total number of Bytes 08 in E2PROM Memory Type (DDR = 07 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] 0D 0B 02 48 00 04 50 50 02 82 04 04 01
Data Sheet
26
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
SPD Contents Table 13 SPD Codes for HYS72D128320GBR-5, HYS72D643[00/20]GBR-5 and HYS72D32300GBR-5 HYS72D128320GBR-5-B HYS72D64300GBR-5-B HYS72D64320GBR-5-B HYS72D32300GBR-5-B 256 MB x72 1 Rank Rev 0.0 HEX 0E 04 1C 01 02 26 C1 60 50 75 50 3C 28 3C 28 40 60 60 40 40 00 37 Rev. 1.1, 2004-04 10102003-01E2-HPA8
Product Type & Organization
1 GByte x72 2 Ranks PC3200R-30331 HEX 0E 04 1C 01 02 26 60 50
512 MB x72 1 Rank PC3200R-30330 Rev 0.0 HEX 0E 04 1C 01 02 26 C1 60 50 75 50 3C 28 3C 28 80 60 60 40 40 00 37
512 MB x72 2 Ranks Rev 0.0 HEX 0E 04 1C 01 02 26 C1 60 50 75 50 3C 28 3C 28 40 60 60 40 40 00 37
Label Code Byte# 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - 40 41 Description Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns]
PC3200R-30330 PC3200R-30330
Jedec SPD Revision Rev 1.0
Component Attributes C0
tCK @ CLmax -1 (Byte 75 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, TCH [ns] tDS [ns] tDH [ns] not used tRCmin [ns] 50 3C 28 3C 28 80 60 60 40 40 00 37
Data Sheet
27
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
SPD Contents Table 13 SPD Codes for HYS72D128320GBR-5, HYS72D643[00/20]GBR-5 and HYS72D32300GBR-5 HYS72D128320GBR-5-B HYS72D64300GBR-5-B HYS72D64320GBR-5-B HYS72D32300GBR-5-B 256 MB x72 1 Rank Rev 0.0 HEX 41 28 28 50 00 00 00 00 15 C1 49 4E 46 49 4E 45 4F xx 37 32 Rev. 1.1, 2004-04 10102003-01E2-HPA8
Product Type & Organization
1 GByte x72 2 Ranks PC3200R-30331 HEX 41 28 28 50 00 01 00 10 5F C1 49 4E 46 49 4E 45 4F xx 37 32
512 MB x72 1 Rank PC3200R-30330 Rev 0.0 HEX 41 28 28 50 00 00 00 00 4E C1 49 4E 46 49 4E 45 4F xx 37 32
512 MB x72 2 Ranks Rev 0.0 HEX 41 28 28 50 00 00 00 00 16 C1 49 4E 46 49 4E 45 4F xx 37 32
Label Code Byte# 42 43 44 45 46 47 48 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 Description tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height not used SPD Revision Checksum of Byte 062 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2) JEDEC ID Code of Infineon (3) JEDEC ID Code of Infineon (4) JEDEC ID Code of Infineon (5) JEDEC ID Code of Infineon (6) JEDEC ID Code of Infineon (7) JEDEC ID Code of Infineon (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2
PC3200R-30330 PC3200R-30330
Jedec SPD Revision Rev 1.0
Data Sheet
28
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
SPD Contents Table 13 SPD Codes for HYS72D128320GBR-5, HYS72D643[00/20]GBR-5 and HYS72D32300GBR-5 HYS72D128320GBR-5-B HYS72D64300GBR-5-B HYS72D64320GBR-5-B HYS72D32300GBR-5-B 256 MB x72 1 Rank Rev 0.0 HEX 44 33 32 33 30 30 47 42 52 35 42 20 20 20 20 20 xx xx xx xx xx xx xx Rev. 1.1, 2004-04 10102003-01E2-HPA8
Product Type & Organization
1 GByte x72 2 Ranks PC3200R-30331 HEX 44 31 32 38 33 32 30
512 MB x72 1 Rank PC3200R-30330 Rev 0.0 HEX 44 36 34 33 30 30 47 42 52 35 42 20 20 20 20 20 xx xx xx xx xx xx xx
512 MB x72 2 Ranks Rev 0.0 HEX 44 36 34 33 32 30 47 42 52 35 42 20 20 20 20 20 xx xx xx xx xx xx xx
Label Code Byte# 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 Description Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9
PC3200R-30330 PC3200R-30330
Jedec SPD Revision Rev 1.0
Part Number, Char 10 47 Part Number, Char 11 42 Part Number, Char 12 52 Part Number, Char 13 37 Part Number, Char 14 42 Part Number, Char 15 20 Part Number, Char 16 20 Part Number, Char 17 20 Part Number, Char 18 20 Module Revision Code xx Test Program Revision Code xx
Module Manufacturing xx Date Year Module Manufacturing xx Date Week Module Serial Number xx (1) Module Serial Number xx (2) Module Serial Number xx (3)
Data Sheet
29
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
SPD Contents Table 13 SPD Codes for HYS72D128320GBR-5, HYS72D643[00/20]GBR-5 and HYS72D32300GBR-5 HYS72D128320GBR-5-B HYS72D64300GBR-5-B HYS72D64320GBR-5-B HYS72D32300GBR-5-B 256 MB x72 1 Rank Rev 0.0 HEX xx 00 HYS72D64320GBR-6-B 512 MB x72 2 Ranks PC2700R- 25330 Rev 0.0 HEX 80 08 07 256 MB x72 1 Rank PC2700R- 25330 Rev 0.0 HEX 80 08 07 Rev. 1.1, 2004-04 10102003-01E2-HPA8 HYS72D32300GBR-6-B
Product Type & Organization
1 GByte x72 2 Ranks PC3200R-30331 HEX
512 MB x72 1 Rank PC3200R-30330 Rev 0.0 HEX xx 00
512 MB x72 2 Ranks Rev 0.0 HEX xx 00
Label Code Byte# 98 Description
PC3200R-30330 PC3200R-30330
Jedec SPD Revision Rev 1.0 Module Serial Number xx (4) 00
99 - 127 not used
Table 14
SPD Codes for HYS72D128320GBR-6-B, HYS72D64300GBR-[6/7]-B, HYS72D64320GBR-6-B and HYS72D32300GBR-6-B HYS72D128320GBR-6-B HYS72D64300GBR-6-B HYS72D64300GBR-7-B 512 MB x72 1 Rank PC2100R- 20330 Rev 0.0 HEX 80 08 07 30
Product Type & Organization
1 GByte x72 2 Ranks PC2700R- 25330 Rev 0.0 HEX
512 MB x72 1 Rank PC2700R- 25330 Rev 0.0 HEX 80 08 07
Label Code Jedec SPD Revision Byte# 0 1 2 Description
Programmed SPD 80 Bytes in E2PROM Total number of 08 Bytes in E2PROM Memory Type (DDR = 07h) 07
Data Sheet
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
SPD Contents Table 14 SPD Codes for HYS72D128320GBR-6-B, HYS72D64300GBR-[6/7]-B, HYS72D64320GBR-6-B and HYS72D32300GBR-6-B HYS72D128320GBR-6-B HYS72D64300GBR-6-B HYS72D64300GBR-7-B HYS72D64320GBR-6-B HYS72D32300GBR-6-B 256 MB x72 1 Rank PC2700R- 25330 Rev 0.0 HEX 0D 0A 01 48 00 04 60 70 02 82 08 08 01 0E 04 Rev. 1.1, 2004-04 10102003-01E2-HPA8
Product Type & Organization
1 GByte x72 2 Ranks PC2700R- 25330 Rev 0.0 HEX 0D 0B
512 MB x72 1 Rank PC2700R- 25330 Rev 0.0 HEX 0D 0B
512 MB x72 1 Rank PC2100R- 20330 Rev 0.0 HEX 0D 0B
512 MB x72 2 Ranks PC2700R- 25330 Rev 0.0 HEX 0D 0A
Label Code Jedec SPD Revision Byte# 3 4 Description Number of Row Addresses Number of Column Addresses Number of DIMM Ranks
5 6 7 8 9 10
02
01 48 00 04 60 70
01 48 00 04 70 75
02 48 00 04 60 70
Data Width (LSB) 48 Data Width (MSB) 00 Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported 04 60 70
11 12 13 14 15 16 17
02 82 04 04 01 0E
02 82 04 04 01 0E 04
02 82 04 04 01 0E 04
02 82 08 08 01 0E 04
Number of Banks 04 on SDRAM Device
Data Sheet
31
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
SPD Contents Table 14 SPD Codes for HYS72D128320GBR-6-B, HYS72D64300GBR-[6/7]-B, HYS72D64320GBR-6-B and HYS72D32300GBR-6-B HYS72D128320GBR-6-B HYS72D64300GBR-6-B HYS72D64300GBR-7-B HYS72D64320GBR-6-B HYS72D32300GBR-6-B 256 MB x72 1 Rank PC2700R- 25330 Rev 0.0 HEX 0C 01 02 26 C0 75 70 00 00 48 30 48 2A 40 75 75 45 45 00 3C 48 Rev. 1.1, 2004-04 10102003-01E2-HPA8
Product Type & Organization
1 GByte x72 2 Ranks PC2700R- 25330 Rev 0.0 HEX 0C 01 02 26 C0 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48
512 MB x72 1 Rank PC2700R- 25330 Rev 0.0 HEX 0C 01 02 26 C0 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 32
512 MB x72 1 Rank PC2100R- 20330 Rev 0.0 HEX 0C 01 02 26 C0 75 75 00 00 50 3C 50 2D 80 90 90 50 50 00 41 4B
512 MB x72 2 Ranks PC2700R- 25330 Rev 0.0 HEX 0C 01 02 26 C0 75 70 00 00 48 30 48 2A 40 75 75 45 45 00 3C 48
Label Code Jedec SPD Revision Byte# 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 Description CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes tCK @ CLmax 0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, TCH [ns] tDS [ns] tDH [ns] not used tRCmin [ns] tRFCmin [ns]
Data Sheet
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
SPD Contents Table 14 SPD Codes for HYS72D128320GBR-6-B, HYS72D64300GBR-[6/7]-B, HYS72D64320GBR-6-B and HYS72D32300GBR-6-B HYS72D128320GBR-6-B HYS72D64300GBR-6-B HYS72D64300GBR-7-B HYS72D64320GBR-6-B HYS72D32300GBR-6-B 256 MB x72 1 Rank PC2700R- 25330 Rev 0.0 HEX 30 28 50 00 00 00 00 0E C1 49 4E 46 49 4E 45 4F xx Rev. 1.1, 2004-04 10102003-01E2-HPA8
Product Type & Organization
1 GByte x72 2 Ranks PC2700R- 25330 Rev 0.0 HEX 30 28 50 00 00 00
512 MB x72 1 Rank PC2700R- 25330 Rev 0.0 HEX 30 28 50 00 00 00 00 47 C1 49 4E 46 49 4E 45 4F xx
512 MB x72 1 Rank PC2100R- 20330 Rev 0.0 HEX 30 32 75 00 00 00 00 03 C1 49 4E 46 49 4E 45 4F xx
512 MB x72 2 Ranks PC2700R- 25330 Rev 0.0 HEX 30 28 50 00 00 00 00 0F C1 49 4E 46 49 4E 45 4F xx
Label Code Jedec SPD Revision Byte# 43 44 45 46 47 48 - 61 62 63 64 65 66 67 68 69 70 71 72 Description tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used not used SPD Revision
DIMM PCB Height 00
Checksum of Byte 48 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2) JEDEC ID Code of Infineon (3) JEDEC ID Code of Infineon (4) JEDEC ID Code of Infineon (5) JEDEC ID Code of Infineon (6) JEDEC ID Code of Infineon (7) JEDEC ID Code of Infineon (8) Module Manufacturer Location C1 49 4E 46 49 4E 45 4F xx
Data Sheet
33
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
SPD Contents Table 14 SPD Codes for HYS72D128320GBR-6-B, HYS72D64300GBR-[6/7]-B, HYS72D64320GBR-6-B and HYS72D32300GBR-6-B HYS72D128320GBR-6-B HYS72D64300GBR-6-B HYS72D64300GBR-7-B HYS72D64320GBR-6-B HYS72D32300GBR-6-B 256 MB x72 1 Rank PC2700R- 25330 Rev 0.0 HEX 37 32 44 33 32 33 30 30 47 42 52 36 42 20 Rev. 1.1, 2004-04 10102003-01E2-HPA8
Product Type & Organization
1 GByte x72 2 Ranks PC2700R- 25330 Rev 0.0 HEX 37 32 44 31 32 38 33 32 30 47 42 52 36 42
512 MB x72 1 Rank PC2700R- 25330 Rev 0.0 HEX 37 32 44 36 34 33 30 30 47 42 52 36 42 20
512 MB x72 1 Rank PC2100R- 20330 Rev 0.0 HEX 37 32 44 36 34 33 30 30 47 42 52 37 42 20
512 MB x72 2 Ranks PC2700R- 25330 Rev 0.0 HEX 37 32 44 36 34 33 32 30 47 42 52 36 42 20
Label Code Jedec SPD Revision Byte# 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Description Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14
Data Sheet
34
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
SPD Contents Table 14 SPD Codes for HYS72D128320GBR-6-B, HYS72D64300GBR-[6/7]-B, HYS72D64320GBR-6-B and HYS72D32300GBR-6-B HYS72D128320GBR-6-B HYS72D64300GBR-6-B HYS72D64300GBR-7-B HYS72D64320GBR-6-B HYS72D32300GBR-6-B 256 MB x72 1 Rank PC2700R- 25330 Rev 0.0 HEX 20 20 20 20 xx xx xx xx xx xx xx xx 00 Rev. 1.1, 2004-04 10102003-01E2-HPA8
Product Type & Organization
1 GByte x72 2 Ranks PC2700R- 25330 Rev 0.0 HEX 20 20 20 20 xx xx xx
512 MB x72 1 Rank PC2700R- 25330 Rev 0.0 HEX 20 20 20 20 xx xx xx
512 MB x72 1 Rank PC2100R- 20330 Rev 0.0 HEX 20 20 20 20 xx xx xx
512 MB x72 2 Ranks PC2700R- 25330 Rev 0.0 HEX 20 20 20 20 xx xx xx
Label Code Jedec SPD Revision Byte# 87 88 89 90 91 92 93 Description Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1) Module Serial Number (2) Module Serial Number (3) Module Serial Number (4)
94
xx
xx
xx
xx
95 96 97 98
xx xx xx xx 00
xx xx xx xx 00
xx xx xx xx 00
xx xx xx xx 00
99 - 127 not used
Data Sheet
35
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
SPD Contents
Table 15
SPD Codes for HYS72D[64/128]320GBR-7-B and HYS72D32300GBR-7-B HYS72D128320GBR-7-B HYS72D64320GBR-7-B HYS72D32300GBR-7-B 256 MB x72 1 Rank PC2100R- 20330 Rev 0.0 HEX 80 08 07 0D 0A 01 48 00 04 70 75 02 82 08 08 01 0E 04 0C 01 02 26 C0 75 75 00 Rev. 1.1, 2004-04 10102003-01E2-HPA8
Product Type & Organization
1 GByte x72 2 Ranks PC2100R- 20330 Rev 0.0 HEX 80 08 07 0D 0B 02 48 00 04 70 75 02 82 04 04 01 0E 04 0C 01 02 26 C0 75 75 00 36
512 MB x72 2 Ranks PC2100R- 20330 Rev 0.0 HEX 80 08 07 0D 0A 02 48 00 04 70 75 02 82 08 08 01 0E 04 0C 01 02 26 C0 75 75 00
Label Code Jedec SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns]
Data Sheet
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
SPD Contents Table 15 SPD Codes for HYS72D[64/128]320GBR-7-B and HYS72D32300GBR-7-B HYS72D128320GBR-7-B HYS72D64320GBR-7-B HYS72D32300GBR-7-B 256 MB x72 1 Rank PC2100R- 20330 Rev 0.0 HEX 00 50 3C 50 2D 40 90 90 50 50 00 41 4B 30 32 75 00 00 00 00 CA C1 49 4E 46 49 4E Rev. 1.1, 2004-04 10102003-01E2-HPA8
Product Type & Organization
1 GByte x72 2 Ranks PC2100R- 20330 Rev 0.0 HEX 00 50 3C 50 2D 80 90 90 50 50 00 41 4B 30 32 75 00 00 00 00 04 C1 49 4E 46 49 4E 37
512 MB x72 2 Ranks PC2100R- 20330 Rev 0.0 HEX 00 50 3C 50 2D 40 90 90 50 50 00 41 4B 30 32 75 00 00 00 00 CB C1 49 4E 46 49 4E
Label Code Jedec SPD Revision Byte# 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 66 67 68 69 Description tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, TCH [ns] tDS [ns] tDH [ns] not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height not used SPD Revision Checksum of Byte 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2) JEDEC ID Code of Infineon (3) JEDEC ID Code of Infineon (4) JEDEC ID Code of Infineon (5) JEDEC ID Code of Infineon (6)
Data Sheet
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
SPD Contents Table 15 SPD Codes for HYS72D[64/128]320GBR-7-B and HYS72D32300GBR-7-B HYS72D128320GBR-7-B HYS72D64320GBR-7-B HYS72D32300GBR-7-B 256 MB x72 1 Rank PC2100R- 20330 Rev 0.0 HEX 45 4F xx 37 32 44 33 32 33 30 30 47 42 52 37 42 20 20 20 20 20 xx xx xx xx xx xx Rev. 1.1, 2004-04 10102003-01E2-HPA8
Product Type & Organization
1 GByte x72 2 Ranks PC2100R- 20330 Rev 0.0 HEX 45 4F xx 37 32 44 31 32 38 33 32 30 47 42 52 37 42 20 20 20 20 xx xx xx xx xx xx 38
512 MB x72 2 Ranks PC2100R- 20330 Rev 0.0 HEX 45 4F xx 37 32 44 36 34 33 32 30 47 42 52 37 42 20 20 20 20 20 xx xx xx xx xx xx
Label Code Jedec SPD Revision Byte# 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Description JEDEC ID Code of Infineon (7) JEDEC ID Code of Infineon (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1) Module Serial Number (2)
Data Sheet
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
SPD Contents Table 15 SPD Codes for HYS72D[64/128]320GBR-7-B and HYS72D32300GBR-7-B HYS72D128320GBR-7-B HYS72D64320GBR-7-B HYS72D32300GBR-7-B 256 MB x72 1 Rank PC2100R- 20330 Rev 0.0 HEX xx xx 00 Rev. 1.1, 2004-04 10102003-01E2-HPA8
Product Type & Organization
1 GByte x72 2 Ranks PC2100R- 20330 Rev 0.0 HEX xx xx 00
512 MB x72 2 Ranks PC2100R- 20330 Rev 0.0 HEX xx xx 00
Label Code Jedec SPD Revision Byte# 97 98 Description Module Serial Number (3) Module Serial Number (4)
99 - 127 not used
Data Sheet
39
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Package Outlines
5
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 2.64 MAX.
A
4 0.1 28.58 0.13
1 2.5 0.1
o0.1 A B C
6.62 2.175 6.35
92
B 0.4
C
1.27 0.1 49.53
64.77 95 x 1.27 = 120.65
3.8 0.13
1.8 0.1 93
0.1 A B C 184
10 17.8
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Figure 6 Package Outlines Raw Card A L-DIM 184-21
Data Sheet
40
Rev. 1.1, 2004-04 10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 4 MAX.
A
4 0.1
1 2.5 0.1
o0.1 A B C
6.62 2.175 6.35
92
28.58 0.13
BC 0.4 1.27 0.1 49.53 95 x 1.27 = 120.65 64.77 1.8 0.1 93 0.1 A B C 184
3.8 0.13
10
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Figure 7
Package Outlines Raw Card B L-DIM 184-23
Data Sheet
41
Rev. 1.1, 2004-04 10102003-01E2-HPA8
17.8
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 4 MAX.
A
4 0.1 28.58 0.13
1 2.5 0.1
o0.1 A B C
6.62 2.175 6.35
92
BC 0.4 1.27 0.1
64.77 95 x 1.27 = 120.65
49.53
3.8 0.13
1.8 0.1 93
0.1 A B C 184
10 17.8
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Figure 8
Package Outline Raw Card C L-DIM 184-22
Data Sheet
42
Rev. 1.1, 2004-04 10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 4 MAX.
A
4 0.1 30.48 0.13
1 2.5 0.1
o0.1 A B C
6.62 2.175 6.35
92
BC 0.4 1.27 0.1
64.77 95 x 1.27 = 120.65
49.53
3.8 0.13
1.8 0.1 93
0.1 A B C
184
10 17.8
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Figure 9 Package Outline Raw card D L-DIM 184-24
Data Sheet
43
Rev. 1.1, 2004-04 10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Application Note
6
Application Note
Power Up and Power Management on DDR Registered DIMMs (according to JEDEC ballot JC-42.5 Item 1173) 184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up and to minimize power consumption during low power mode. One feature is externally controlled via a systemgenerated RESET signal; the second is based on module detection of the input clocks. These enhancements permit the modules to power up with SDRAM outputs in a High-Z state (eliminating risk of high current dissipations and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-Locked Loop) when the memory is in Self-Refresh mode. The new RESET pin controls power dissipation on the module's registers and ensures that CKE and other SDRAM inputs are maintained at a valid `low' level during power-up and self refresh. When RESET is at a low level, all the register outputs are forced to a low level, and all differential register input receivers are powered down, resulting in very low register power consumption. The RESET pin, located on DIMM tab #10, is driven from the system as an asynchronous signal according to the attached details. Using this function also permits the system and DIMM clocks to be stopped during memory Self Refresh operation, while ensuring that the SDRAMs stay in Self Refresh mode. Table 16 RESET Truth Table Register Inputs RESET H H H H L CK Rising Rising L or H High Z X or Hi-Z CK Falling Falling L or H High Z X or Hi-Z Data in (D) H L X X X or Hi-Z Register Outputs Data out (Q) H L Qo Illegal input conditions L
X: Don't care, Hi-Z: High Impedance, Qo: Data latched at the previous of CK rising and CK falling As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are maintained low at the SDRAM pins (CKE being one of the 'Q' signals at the register output). Holding CKE low maintains a high impedance state on the SDRAM DQ, DQS and DM outputs -- where they will remain until activated by a valid `read' cycle. CKE low also maintains SDRAMs in Self Refresh mode when applicable. The DDR PLL devices automatically detect clock activity above 20MHz. When an input clock frequency of 20MHz or greater is detected, the PLL begins operation and initiates clock frequency lock (the minimum operating frequency at which all specifications will be met is 95MHz). If the clock input frequency drops below 20MHz (actual detect frequency will vary by vendor), the PLL VCO (Voltage Controlled Oscillator) is stopped, outputs are made High-Z, and the differential inputs are powered down -- resulting in a total PLL current consumption of less than 1mA. Use of this low power PLL function makes the use of the PLL RESET (or G pin) unnecessary, and it is tied inactive on the DIMM. This application note describes the required and optional system sequences associated with the DDR Registered DIMM 'RESET' function. It is important to note that all references to CKE refer to both CKE0 and CKE1 for a 2bank DIMM. Because RESET applies to all DIMM register devices, it is therefore not possible to uniquely control CKE to one physical DIMM bank through the use of the RESET pin.
Data Sheet
44
Rev. 1.1, 2004-04 10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Application Note Power-Up Sequence with RESET -- Required 1. The system sets RESET at a valid low level. This is the preferred default state during power-up. This input condition forces all register outputs to a low state independent of the condition on the register inputs (data and clock), ensuring that CKE is at a stable low-level at the DDR SDRAMs. 2. The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR SDRAMs. 3. Stabilization of Clocks to the SDRAM The system must drive clocks to the application frequency (PLL operation is not assured until the input clock reaches 20 MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. When a stable clock is present at the SDRAM input (driven from the PLL), the DDR SDRAM requires 200 sec prior to SDRAM operation. 4. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the JEDEC initialization sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs. 5. The system switches RESET to a logic `high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, setting the RESET timing in relation to a specific clock edge is not required (during this period, register inputs must remain stable). 6. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows their clock receivers, data input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in step 5. It is also a functional requirement that the registers maintain a low state at the CKE outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time (t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to accept an input signal, is specified in the register and DIMM do-umentation. 7. The system can begin the JEDEC-defined DDR SDRAM power-up sequence (according to the JEDECpproved initialization sequence). Self Refresh Entry (RESET low, clocks powered off) -- Optional Self Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down and the clocks are off. This mode allows the DDR SDRAMs on the DIMM to retain data without external clocking. Self Refresh mode is an ideal time to utilize the RESET pin, as this can reduce register power consumption (RESET low deactivates register CK and CK, data input receivers, and data output drivers). 1. 1. The system applies Self Refresh entry command. (CKELow, CSLow, RAS Low, CAS Low, WE High) Note: Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input conditions to the SDRAM are Don't Cares-- with the exception of CKE. 2. The system sets RESET at a valid low level. This input condition forces all register outputs to a low state, independent of the condition on the registerm inputs (data and clock), and ensures that CKE, and all other control and address signals, are a stable low-level at the DDR SDRAMs. Since the RESET signal is asynchronous, setting the RESET timing in relation to a specific clock edge is not required. 3. The system turns off clock inputs to the DIMM. (Optional) a. In order to reduce DIMM PLL current, the clock inputs to the DIMM are turned off, resulting in High-Z clock
Data Sheet
45
Rev. 1.1, 2004-04 10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Application Note inputs to both the SDRAMs and the registers. This must be done after the RESET deactivate time of the register (t (INACT). The deactivate time defines the time in which the clocks and the control and address signals must maintain valid levels after RESET low has been applied and is specified in the register and DIMM documentation. b.The system may release DIMM address and control inputs to High-Z. This can be done after the RESET deactivate time of the register. The deactivate time defines the time in which the clocks and the control and the address signals must maintain valid levels after RESET low has been applied. It is highly recommended that CKE continue to remain low during this operation. 4. The DIMM is in lowest power Self Refresh mode. Self Refresh Exit (RESET low, clocks powered off) -- Optional 1. Stabilization of Clocks to the SDRAM. The system must drive clocks to the application frequency (PLL operation is not assured until the input clock reaches ~20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. 2. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the JEDEC Self Refresh Exit sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs, to be consistent with the state of the register outputs. 3. The system switches RESET to a logic `high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, RESET timing relationship to a specific clock edge is not required (during this period, register inputs must remain stable). 4. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in Step 2. It is also a functional requirement that the registers maintain a low state at the CKE outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time (t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to accept an input signal, is specified in the register and DIMM do-umentation. 5. System can begin the JEDEC-defined DDR SDRAM Self Refresh Exit Procedure. Self Refresh Entry (RESET low, clocks running) -- Optional Although keeping the clocks running increases power consumption from the on-DIMM PLL during self refresh, this is an alternate operating mode for these DIMMs. 1. 1. System enters Self Refresh entry command. (CKE Low, CS Low, RAS Low, CAS Low, WE High) Note: Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input conditions to the SDRAM are Don't Cares -- with the exception of CKE. 2. The system sets RESET at a valid low level. This input condition forces all register outputs to a low state, independent of the condition on the data and clock register inputs, and ensures that CKE is a stable low-level at the DDR SDRAMs. 3. The system may release DIMM address and control inputs to High-Z. This can be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time describes the time in which the clocks and the control and the address signals must maintain valid levels after RESET low has been applied. It is highly recommended that CKE continue to remain low during the operation. 4. The DIMM is in a low power, Self Refresh mode.
Data Sheet
46
Rev. 1.1, 2004-04 10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules
Application Note Self Refresh Exit (RESET low, clocks running) -- Optional 1. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the Self Refresh Exit sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs. 2. The system switches RESET to a logic 'high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, it does not need to be tied to a particular clock edge (during this period, register inputs must continue to remain stable). 3. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in Step 1. It is also a functional requirement that the registers maintain a low state at the CKE outputs in order to guarantee that the DDR SDRAMs continue to receive a low level on CKE. This activation time, from asynchronous switching of RESET from low to high, until the registers are stable and ready to accept an input signal, is t (ACT ) as specified in the register and DIMM documentation. 4. The system can begin JEDEC defined DDR SDRAM Self Refresh Exit Procedure. Self Refresh Entry/Exit (RESET high, clocks running) -- Optional As this sequence does not involve the use of the RESET function, the JEDEC standard SDRAM specification explains in detail the method for entering and exiting Self Refresh for this case. Self Refresh Entry (RESET high, clocks powered off) -- Not Permissible In order to maintain a valid low level on the register output, it is required that either the clocks be running and the system drive a low level on CKE, or the clocks are powered off and RESET is asserted low according to the sequence defined in this application note. In the case where RESET remains high and the clocks are powered off, the PLL drives a High-Z clock input into the register clock input. Without the low level on RESET an unknown DIMM state will result.
Data Sheet
47
Rev. 1.1, 2004-04 10102003-01E2-HPA8
www.infineon.com
Published by Infineon Technologies AG

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